404: Not Found{"id":4506,"date":"2023-05-15T16:10:33","date_gmt":"2023-05-15T16:10:33","guid":{"rendered":"https:\/\/gigora.com\/intel-arm-collaboration-is-under-way\/"},"modified":"2023-05-15T16:10:33","modified_gmt":"2023-05-15T16:10:33","slug":"intel-arm-collaboration-is-under-way","status":"publish","type":"post","link":"https:\/\/gigora.com\/intel-arm-collaboration-is-under-way\/","title":{"rendered":"Intel-Arm Collaboration Is Under Way"},"content":{"rendered":"<p> [ad_1]<br \/>\n<\/p>\n<div>\n<p>\t\t\t\t\t\/\/php echo do_shortcode(&#8216;[responsivevoice_button voice=&#8221;US English Male&#8221; buttontext=&#8221;Listen to Post&#8221;]&#8217;) ?&gt;<br \/>\n\t\t\t\t\t<!-- EET_Top_Leaderboard --><\/p>\n<p>Intel Foundry Services and Arm agreed last month to optimize Arm\u2019s IP for Intel\u2019s upcoming 18A process technology (1.8 nm). The collaboration will focus on mobile designs and will undertake design technology co-optimization (DTCO) and system technology co-optimization (STCO), which means that Arm\u2019s IP will be optimized both for Intel\u2019s forthcoming production node and for the company\u2019s advanced packaging technologies.<\/p>\n<p>Intel Foundry Services and Arm will jointly fine-tune Arm\u2019s IP using the DTCO methodology for Intel\u2019s 18A manufacturing process to optimize performance, power and costs of upcoming designs. One of the key fruits of this collaboration will be development of \u201can Arm-based mobile SoC and silicon technology demonstration and reference platform for chip designs,\u201d which is a rather broad definition of the work.<\/p>\n<p>Meanwhile, Intel and Arm confirm that the work has commenced.<\/p>\n<p>\u201cThe work will validate the performance, power and area utilization of Arm SoC designs on the Intel 18A process,\u201d a spokesperson for Intel told EE Times.<\/p>\n<p>\u201cWe are building custom IP to ensure optimal power, performance and area for Arm-based SoC design,\u201d a spokesperson for Arm explained to EE Times. \u201cWith this announcement, we enable one more option to our licensees to choose from when they target advanced nodes for Arm-based SoC design.\u201d<\/p>\n<figure id=\"attachment_1404114\" aria-describedby=\"caption-attachment-1404114\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a rel=\"nofollow noopener\" href=\"https:\/\/www.eetimes.com\/system-co-optimization-hierarchy\/\" target=\"_blank\"><img fetchpriority=\"high\" decoding=\"async\" class=\"wp-image-1404114 size-large jetpack-lazy-image\" title=\"Hierarchies in system technology co-optimization\" alt=\"Hierarchies in system technology co-optimization.\" width=\"640\" height=\"497\" data-recalc-dims=\"1\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/system-co-optimization-hierarchy.png?w=640&amp;is-pending-load=1#038;resize=640%2C497\" srcset=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\"\/><noscript><img data-lazy-fallback=\"1\" decoding=\"async\" class=\"wp-image-1404114 size-large\" title=\"Hierarchies in system technology co-optimization\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/system-co-optimization-hierarchy.png?w=640&amp;resize=640%2C497\" alt=\"Hierarchies in system technology co-optimization.\" width=\"640\" height=\"497\" data-recalc-dims=\"1\"\/><\/noscript><\/a><figcaption id=\"caption-attachment-1404114\" class=\"wp-caption-text\">Hierarchies in system technology co-optimization. The differences between device optimization, DTCO, 3DIC and STCO are illustrated. (Source: Intel)<\/figcaption><\/figure>\n<h3><strong>In search of new customers<\/strong><\/h3>\n<p>While initially the \u201cmultigeneration\u201d collaboration will focus on mobile SoC projects and appropriate Arm IP (e.g., Cortex-A CPU IP, Mali GPU IP, etc.), the two companies said that the scope of the collaboration may be expanded to automotive, aerospace, data center (e.g., Neoverse), IoT and government applications. While \u201cgovernment applications\u201d is a rather ambiguous term, keep in mind that Intel\u2019s <a rel=\"nofollow\" href=\"https:\/\/www.eetimes.com\/intel-foundrys-no-1-customer-u-s-dod-targets-gaa\/\">18A has already been selected by the U.S. Department of Defense<\/a>, so perhaps it will be a little easier for Arm licensees to address the needs of the U.S. Army with optimized Arm IP.<\/p>\n<p>Meanwhile, it is hard to overestimate the general importance of the Intel Foundry-Arm announcement, as it ensures that IFS will be able to produce <a rel=\"nofollow\" href=\"https:\/\/www.eetimes.com\/distributed-architecture-puts-the-reality-in-ar\/\">SoCs<\/a> based on optimized Arm IP, just like its rivals from TSMC and Samsung Foundry.<\/p>\n<p>On the other hand, Arm needs to ensure that its cores can be made by as many chip producers as possible on as many fabrication technologies as possible.<\/p>\n<p>\u201cArm needs to make sure its cores are validated on as many process nodes as possible, but for Intel, it gives them a selling point for lots of Arm ecosystem players, which has done very well for TSMC,\u201d said Ian Cutress, principal analyst at More Than Moore. \u201cIntel is looking to grow customers by orders of magnitude, whereas for Arm, this is \u2018another step.\u2019\u201d<\/p>\n<p>\u201cIFS wants to have as much IP as possible to enable customers to build products,\u201d said David Kanter, president of Real World Tech and inference and power co-chair at\u00a0<a rel=\"nofollow\" href=\"https:\/\/mlperf.org\/\">MLPerf<\/a>. \u201cThe more IP that is available on IFS, the lower the friction for a customer.\u201d<\/p>\n<p>\u201cThis helps align Intel\u2019s foundries with the needs of the industry, which is a focus on performance efficiency,\u201d said Jim McGregor, principal analyst at Tirias Research. \u201cIt also makes the foundry market more competitive by offering another leading-edge foundry.\u201d<\/p>\n<p>The scope of the collaboration is currently limited to mobile SoCs, which may be somewhat surprising given Intel\u2019s focus on data center hardware in recent years and its experience with large chips in general, but it makes a lot of sense both for Arm and Intel Foundry, as smartphone SoCs are among the largest revenue sources for Arm and represent a good opportunity for Intel Foundry.<\/p>\n<p>\u201cRight now, with Softbank and IPO, Arm is limiting the projects it is doing, so it is picking and choosing the highest-benefit opportunities,\u201d Cutress said. \u201cMobile SoCs is a good target because IFS only really has high-performance nodes to offer, and die sizes are small [~100\u2013150 mm<sup>2<\/sup>], which are better for yield ramp compared with large, 700-mm<sup>2<\/sup> data center silicon. Automotive does not always need leading edge, so mobile SoCs are good. If we look at TSMC, 34% of its revenue is smartphones and 44% is HPC [mobile and performance], so IFS\/Arm going after mobile IP validation makes sense.\u201d<\/p>\n<h3><strong>Not only mobile<\/strong><\/h3>\n<p>Intel itself considers its 18A process as the node that will have an indisputable lead when it comes to performance, power and transistor density. The company originally planned that its 18A manufacturing technology would be the first to use ASML\u2019s High-NA Twinscan EXE EUV scanners, with a 0.55 numerical aperture sometime in 2025, but eventually, the company disclosed that it could use existing 0.33-NA EUV tools with double patterning instead of next-generation machines in the second half of 2024. Meanwhile, to reduce EUV double patterning and optimize 20A and 18A costs, the company will adopt <a rel=\"nofollow\" href=\"https:\/\/www.eetimes.com\/pattern-shaping-system-speeds-up-chip-production\/\">Applied Materials\u2019 Centura Sculpta pattern-shaping tool<\/a>.<\/p>\n<p>If Intel manages to provide the highest performance efficiency and transistor density with its 18A manufacturing process and offer it at good financial terms, fabless chip designers will be inclined to use it. Furthermore, with optimized standard Arm IP, the process technology promises to be even more attractive for SoC developers.<\/p>\n<p>\u201cThe goal of supporting Arm cores is that they are used across a wide range of products and are a \u2018standard building block\u2019 for many SoCs,\u201d Kanter noted.<\/p>\n<p>While the announcement itself is very general, the collaboration promises to provide a lot of possibilities for Arm\u2019s licensees, including Qualcomm, which has already announced plans to use Intel\u2019s 18A fabrication process but never disclosed for what kinds of products. MediaTek is another major mobile SoC developer signed up to use IFS\u2019s capacity, but it has yet to show interest toward Intel\u2019s 1.8-nm\u2013class production node. There could be other less obvious beneficiaries from the IFS-Arm announcement, analysts said.<\/p>\n<p>\u201cQualcomm has expressed interest, but until a company starts handing over money and investing design teams, I am skeptical,\u201d Cutress said. \u201cMediaTek has expressed interest, but not so much on mobile SoCs so far. That leaves few other major players\u2014Apple [not until Intel has leadership], Samsung [would be weird but not impossible] and Unisoc [might be a way around the issues they are having with the U.S. government].\u201d<\/p>\n<p>Qualcomm already uses customized high-performance Arm cores in its Snapdragon SoCs, and in the coming years, the company plans to adopt highly custom Nuvia-developed Arm microarchitecture across a range of products. Therefore, it is less likely to be interested in implementation of standard high-performance Arm Cortex cores, but it can still take advantage of Arm technology optimized for Intel\u2019s 18A.<\/p>\n<p>\u201cEven in the case of Qualcomm, many mobile SoCs use smaller cores either as user-visible processors [e.g., the \u2018little\u2019 core] or as a service processor,\u201d Real World Tech\u2019s Kanter said. \u201cIn the mobile world, MediaTek tends to use standard Arm cores throughout their product line.\u201d<\/p>\n<p>\u201cQualcomm is the obvious [beneficiary] that comes to mind, but Apple could benefit from it,\u201d Tirias Research\u2019s McGregor said. \u201cMediaTek, which has a modem partnership with Intel, could benefit from it. Google could benefit from it. Other handset OEMs considering making their own chips could also benefit from it.\u201d<\/p>\n<p>In fact, there are a lot of non-mobile applications\u2014aimed at anything from automotive to data centers\u2014that can benefit from standard Arm cores optimized for Intel\u2019s 18A node, analysts from More Than Moore and Real World Tech said.<\/p>\n<p>\u201cThere is also a lot of \u2018mobile SoC-like\u2019 ASICs out there that you might not think of: IPMI silicon, ACAPs Xilinx\/hardened FPGAs, controllers, etc.,\u201d Cutress said. \u201cRequirements on [automotive infotainment] silicon are not as strict.\u201d<\/p>\n<p>\u201cArm IP is potentially useful in automotive infotainment,\u201d Kanter said. \u201cJust look at GM\u2019s adoption of Android. Android runs best on Arm.\u201d<\/p>\n<p>\u201cThe mobile segment is just the tip of the iceberg,\u201d McGregor said. \u201cThe CE and embedded markets account for even more Arm components.\u201d<\/p>\n<p>In fact, Intel Foundry and Arm collaboration could quickly extend to more demanding data center applications, he said.<\/p>\n<p>\u201cThey can extend it very quickly,\u201d McGregor added. \u201cYou have to remember that Intel is and has been an Arm licensee for many, many years. Intel is familiar with the architecture. The only limitation is demand. If the opportunity arises, I am sure we will see these products running at Intel even though they will compete with other Intel products.\u201d<\/p>\n<h3><strong>DTCO meets GAA transistors and backside power delivery<\/strong><\/h3>\n<p>When it comes to foundries, DTCO methodologies have been around for some time, so IFS is certainly not the first here. Actually, most of Intel\u2019s own CPU cores are architected for particular production nodes, representing a good example of DTCO advantages when it comes to frequencies and power, albeit at an IDM, so Intel is certainly not new to this methodology as well.<\/p>\n<p>Intel\u2019s 18A fabrication process will be the company\u2019s second node (after 20A) to adopt gate-all-around (GAA) transistors that the company calls RibbonFET and backside power delivery network (PDN), branded as PowerVia. Intel\u2019s 20A and 18A are two fabrication technologies that are developed both for Intel itself and for IFS customers. Furthermore, both provide an abundance of options for DTCO.<\/p>\n<figure id=\"attachment_1404112\" aria-describedby=\"caption-attachment-1404112\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a rel=\"nofollow noopener\" href=\"https:\/\/www.eetimes.com\/intel-ribbonfet-2\/\" target=\"_blank\"><img decoding=\"async\" class=\"wp-image-1404112 size-large jetpack-lazy-image\" title=\"Intel\u2019s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint\" alt=\"Intel\u2019s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint.\" width=\"640\" height=\"312\" data-recalc-dims=\"1\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/intel-ribbonfet.png?w=640&amp;is-pending-load=1#038;resize=640%2C312\" srcset=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\"\/><noscript><img loading=\"lazy\" data-lazy-fallback=\"1\" decoding=\"async\" loading=\"lazy\" class=\"wp-image-1404112 size-large\" title=\"Intel\u2019s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/intel-ribbonfet.png?w=640&amp;resize=640%2C312\" alt=\"Intel\u2019s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint.\" width=\"640\" height=\"312\" data-recalc-dims=\"1\"\/><\/noscript><\/a><figcaption id=\"caption-attachment-1404112\" class=\"wp-caption-text\">Intel\u2019s RibbonFET GAA transistor architecture stacks four nanoribbons to achieve the same drive current as multiple fins, but in a small footprint. (Source: Intel)<\/figcaption><\/figure>\n<p>GAAFETs offer several key advantages compared with planar transistors and FinFETs, such as significantly minimized leakage current, as the gates now surround all four sides of the channel.<\/p>\n<p>Also, in GAA transistors, it is possible to alter the nanosheets\u2019 width for a specific production process or even within a particular chip design, enabling the fine-tuning of performance (with increased width), energy consumption (with reduced width) and die area.<\/p>\n<p>For mobile SoC designs, GAA transistor\u2019s reduced leakage current is an indisputable benefit. Tailoring transistor architecture for mobile designs further could enable additional benefits when it comes to power and performance. Meanwhile, adjusting standard cells, developing mobile-specific libraries and implementing Arm IP on Intel\u2019s 18A should enable further performance, power, area and cost optimizations on the transistor level. Unfortunately, Intel Foundry and Arm have not confirmed any specifics related to transistor design optimization.<\/p>\n<p>Feeding transistors has been a challenge on thinner nodes for a while due to <a rel=\"nofollow\" href=\"https:\/\/www.eetimes.com\/applieds-tungsten-process-fights-resistance\/\">increasing contact resistance<\/a> and IR drop, resulting in lost energy, lower performance and high temperatures. Backside PDN (dubbed PowerVia by Intel) moves power wires away from data I\/O wires, simplifying connectivity and enabling a more sophisticated PDN.<\/p>\n<p>\u201cIn general, by eliminating the need for power routing on the front side of the wafer, more resources become available to optimize signal routing and reduce delay,\u201d the Intel spokesperson said. \u201cThis enables us to optimize for performance, power or area depending on the product needs.\u201d<\/p>\n<figure id=\"attachment_1404111\" aria-describedby=\"caption-attachment-1404111\" style=\"width: 578px\" class=\"wp-caption aligncenter\"><a rel=\"nofollow noopener\" href=\"https:\/\/www.eetimes.com\/intel-powervia-2\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-1404111 size-large jetpack-lazy-image\" title=\"Intel\u2019s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size\" alt=\"Intel\u2019s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size.\" width=\"578\" height=\"473\" data-recalc-dims=\"1\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/intel-powervia.png?w=578&amp;is-pending-load=1#038;resize=578%2C473\" srcset=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\"\/><noscript><img loading=\"lazy\" data-lazy-fallback=\"1\" decoding=\"async\" loading=\"lazy\" class=\"wp-image-1404111 size-large\" title=\"Intel\u2019s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/intel-powervia.png?w=578&amp;resize=578%2C473\" alt=\"Intel\u2019s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size.\" width=\"578\" height=\"473\" data-recalc-dims=\"1\"\/><\/noscript><\/a><figcaption id=\"caption-attachment-1404111\" class=\"wp-caption-text\">Intel\u2019s backside PDN, PowerVia, that separates power and signal lines and shrinks the standard cell size. Power wires are placed beneath the transistor layer, on the backside of the wafer. (Source: Intel)<\/figcaption><\/figure>\n<p>Power delivery tends to differ from chip design to chip design.<\/p>\n<p>For example, CPUs for client and data center processors are customized to meet different performance requirements, and therefore, they need different PDNs. Server processors are capable of handling heavy workloads steadily and can briefly enhance their clocks when demand peaks.<\/p>\n<p>On the other hand, client CPUs are optimized for burst behavior in general, as they usually remain inactive or work under low loads\u2014but when a resource-intensive workload is launched, these processors need to quickly (within microseconds) boost their performance from idle to maximum speed, sometimes even surpassing it, to ensure smooth user experience. Smartphone SoCs are designed to respond to demands even quicker, and they need their own PDN design.<\/p>\n<p>Optimizing the PowerVia PDN for Arm IP aimed at smartphone SoCs could bring numerous advantages in terms of performance and power consumption when compared with Intel\u2019s vanilla PowerVia PDN that is likely designed to serve a wide range of applications. Again, formally, Intel Foundry and Arm did not confirm plans to tailor RibbonFETs and PowerVia for standard mobile Arm IP as parts of the ongoing collaborative work.<\/p>\n<p>\u201cI would expect Intel\u2019s GAA to be higher-performance than other foundry options\u2014in part because of the adoption of PowerVia [and also differences in transistor implementation],\u201d Kanter explained. \u201cSo that would potentially translate into better frequency or lower power at similar frequencies. Intel\u2019s PowerVia is part of 20A and 18A, so I would expect the optimization of Arm IP for Intel\u2019s process would include PowerVia as well. PowerVia generally seems likely to provide a small performance benefit through better power delivery [say, 3% to 7%] and a nice area reduction [15% to 20%], based on an analysis I have seen.\u201d<\/p>\n<p>Cutress chimed in: \u201cWhile the collaboration between Intel Foundry and Arm will bring a number of benefits to customers planning to implement Arm\u2019s mobile IP, IFS is willing to work closely with every big-enough customer to improve PPA.<\/p>\n<p>\u201cNothing specific in Arm means Intel\u2019s GAA would get a benefit; the transistor and the architecture are independent,\u201d he added. \u201cI think IFS will do what it can to give its primary customers additional benefits, especially if it is a big player [Apple, Qualcomm], regardless of the chip or the architecture.\u201d<\/p>\n<p>McGregor said he does not see any specific benefit to Arm over other architectures: \u201cThe advancements in semiconductor\/transistor design will be a benefit to the entire industry.\u201d<\/p>\n<figure id=\"attachment_1404107\" aria-describedby=\"caption-attachment-1404107\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a rel=\"nofollow noopener\" href=\"https:\/\/www.eetimes.com\/5-client-2\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-1404107 size-large jetpack-lazy-image\" title=\"An example of multi-tile client system-in-package\" alt=\"An example of multi-tile client system-in-package.\" width=\"640\" height=\"313\" data-recalc-dims=\"1\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/5-client-1.jpg?w=640&amp;is-pending-load=1#038;resize=640%2C313\" srcset=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\"\/><noscript><img loading=\"lazy\" data-lazy-fallback=\"1\" decoding=\"async\" loading=\"lazy\" class=\"wp-image-1404107 size-large\" title=\"An example of multi-tile client system-in-package\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/5-client-1.jpg?w=640&amp;resize=640%2C313\" alt=\"An example of multi-tile client system-in-package.\" width=\"640\" height=\"313\" data-recalc-dims=\"1\"\/><\/noscript><\/a><figcaption id=\"caption-attachment-1404107\" class=\"wp-caption-text\">An example of multi-tile client system-in-package (Source: Intel)<\/figcaption><\/figure>\n<p>Another detail that Intel Foundry and Arm mentioned in prepared remarks was intention to optimize the target platforms \u201cfrom applications and software through package and silicon,\u201d essentially implying STCO. While Intel admits that both EMIB (2.5D) and Foveros (3D) packaging technologies are in the cards, the company is not ready to share any additional details.<\/p>\n<p>\u201cThe collaboration would take both 2.5D and 3D packaging technologies into consideration,\u201d Intel said.<\/p>\n<p>Bringing disaggregated designs to the mobile world, which has been focused on highly integrated SoCs for a while, will mark a milestone for the industry. Though it remains to be seen what exactly Intel and Arm plan to do here, as the framework of the announcement is currently limited to Intel\u2019s 18A production node, whereas a disaggregated design implies usage of several nodes to optimize costs. Furthermore, the costs of advanced packaging are very high now, analysts note.<\/p>\n<p>Qualcomm presented on the topic of chiplet strategies and packaging at IEEE conferences in the past two years, Cutress said, adding, \u201cIt will happen, if not in smartphones, then laptops, where there is z-height available. The main point of contention is cost\u2014chiplet packaging is still very expensive.\u201d<\/p>\n<p>Kanter said advanced packaging in mobile will depend on cost: \u201cRight now, most advanced packaging techniques are relatively expensive to implement. Look at the cost delta for 3D stacking. Once the benefits become greater or we can reduce cost through more mature flows, that could enable more advanced mobile packaging.\u201d<\/p>\n<p>McGregor said disaggregated mobile SoC designs are not in the near future: \u201cYou have to remember that there are size, power, size and cost constraints for mobile. Thus, there are still advantages to having a single die. At least not until the [advanced packaging] cost comes down or the economics of having multiple dies change.\u201d<\/p>\n<p>In fact, Arm also says that while disaggregation of mobile SoCs is possible, it must be evaluated very carefully.<br \/>\u201cThere are many factors in play,\u201d the Arm spokesperson said. \u201cThe cost structure in mobile needs to be evaluated, and importantly, RTL needs to be optimized to ensure the disaggregation and package technology can be taken advantage of.\u201d<\/p>\n<p>But STCO will likely not be limited to packaging only and will involve everything from thermal management to production flows, Kanter said.<\/p>\n<p>\u201cI think STCO encompasses more than just packaging,\u201d he said. \u201cPart of it is integrating thermal management, power delivery and packaging into the overall manufacturing flows.\u201d<\/p>\n<figure id=\"attachment_1404113\" aria-describedby=\"caption-attachment-1404113\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a rel=\"nofollow noopener\" href=\"https:\/\/www.eetimes.com\/intel-stco-system-architecture\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-1404113 size-large jetpack-lazy-image\" title=\"System technology co-optimization of a computing system\" alt=\"System technology co-optimization of a computing system.\" width=\"640\" height=\"656\" data-recalc-dims=\"1\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/intel-stco-system-architecture.png?w=640&amp;is-pending-load=1#038;resize=640%2C656\" srcset=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\"\/><noscript><img loading=\"lazy\" data-lazy-fallback=\"1\" decoding=\"async\" loading=\"lazy\" class=\"wp-image-1404113 size-large\" title=\"System technology co-optimization of a computing system\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/intel-stco-system-architecture.png?w=640&amp;resize=640%2C656\" alt=\"System technology co-optimization of a computing system.\" width=\"640\" height=\"656\" data-recalc-dims=\"1\"\/><\/noscript><\/a><figcaption id=\"caption-attachment-1404113\" class=\"wp-caption-text\">System technology co-optimization of a computing system (Source: Intel)<\/figcaption><\/figure>\n<h3><strong>Broad geography<\/strong><\/h3>\n<p>One of the advantages that Intel expects IFS to have over competitors is that it is going to have 18A-capable production capacity both in the U.S. and Europe, which will enable IFS\u2019s customers to diversify their supply chains.<\/p>\n<figure id=\"attachment_1404110\" aria-describedby=\"caption-attachment-1404110\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a rel=\"nofollow noopener\" href=\"https:\/\/www.eetimes.com\/intel-oregon-moore-park-at-ra-2\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-1404110 size-large jetpack-lazy-image\" title=\"An Intel fab in Oregon\" alt=\"An Intel fab in Oregon.\" width=\"640\" height=\"360\" data-recalc-dims=\"1\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/Intel-Oregon-Moore-Park-at-RA-2.jpg?w=640&amp;is-pending-load=1#038;resize=640%2C360\" srcset=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\"\/><noscript><img loading=\"lazy\" data-lazy-fallback=\"1\" decoding=\"async\" loading=\"lazy\" class=\"wp-image-1404110 size-large\" title=\"An Intel fab in Oregon\" src=\"https:\/\/www.eetimes.com\/wp-content\/uploads\/Intel-Oregon-Moore-Park-at-RA-2.jpg?w=640&amp;resize=640%2C360\" alt=\"An Intel fab in Oregon.\" width=\"640\" height=\"360\" data-recalc-dims=\"1\"\/><\/noscript><\/a><figcaption id=\"caption-attachment-1404110\" class=\"wp-caption-text\">An Intel fab in Oregon (Source: Intel)<\/figcaption><\/figure>\n<p>Because the current collaboration is limited to Arm\u2019s mobile IP, whereas leading mobile SoC developers are located in the U.S. (Apple, Qualcomm), Taiwan (MediaTek) and China (Unisoc), it remains to be seen whether it is important for them to produce their SoCs in the U.S. or Europe, keeping in mind that actual devices will still be assembled in China, India or southeast Asian countries.<\/p>\n<p>Yet, given the current geopolitical tensions, a diversified supply chain may be an advantage, per se, so making leading-edge chips on 18A node both in the U.S. and Europe (eventually) is an indisputable trump card that Intel Foundry will have, Kanter and McGregor said.<\/p>\n<p>\u201cAbility to produce both in the U.S. and Europe is an advantage, especially for military\/government applications,\u201d McGregor said.<\/p>\n<\/p><\/div>\n<p><script type=\"text\/javascript\">\n!function(f,b,e,v,n,t,s){if(f.fbq)return;n=f.fbq=function(){n.callMethod?\nn.callMethod.apply(n,arguments):n.queue.push(arguments)};if(!f._fbq)f._fbq=n;\nn.push=n;n.loaded=!0;n.version='2.0';n.queue=[];t=b.createElement(e);t.async=!0;\nt.src=v;s=b.getElementsByTagName(e)[0];s.parentNode.insertBefore(t,s)}(window,\ndocument,'script','https:\/\/connect.facebook.net\/en_US\/fbevents.js');\n<\/script><script>\n(function(d, s, id) {\n    var js, fjs = d.getElementsByTagName(s)[0];\n    if (d.getElementById(id)) return;\n    js = d.createElement(s); js.id = id;\n    js.src = \"\/\/connect.facebook.net\/en_US\/all.js#xfbml=1&appId=133355186775047\";\n    fjs.parentNode.insertBefore(js, fjs);\n}(document, 'script', 'facebook-jssdk'));\n<\/script><br \/>\n<br \/>[ad_2]<br \/>\n<br \/><a href=\"https:\/\/www.eetimes.com\/experts-weigh-impact-of-intel-arm-collaboration\/\">Source link <\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>[ad_1] \/\/php echo do_shortcode(&#8216;[responsivevoice_button voice=&#8221;US English Male&#8221; buttontext=&#8221;Listen to Post&#8221;]&#8217;) ?&gt; Intel Foundry Services and Arm agreed last month to optimize Arm\u2019s IP for Intel\u2019s upcoming 18A process technology (1.8 nm). The collaboration will focus on mobile designs and will undertake design technology co-optimization (DTCO) and system technology co-optimization (STCO), which means that Arm\u2019s IP&hellip;<\/p>\n","protected":false},"author":1,"featured_media":4507,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[38],"tags":[600,64,65,63,599],"class_list":["post-4506","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-electronics","tag-collaboration","tag-electronic-devices","tag-electronic-engineering","tag-electronics","tag-intelarm","category-38","description-off"],"_links":{"self":[{"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/posts\/4506"}],"collection":[{"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/comments?post=4506"}],"version-history":[{"count":0,"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/posts\/4506\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/media\/4507"}],"wp:attachment":[{"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/media?parent=4506"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/categories?post=4506"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/gigora.com\/wp-json\/wp\/v2\/tags?post=4506"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}